Each memory cell in a dual-port static random access memory (SRAM) macro or chip is a buffer or flip-flop, and data is retained as long as power is maintained to the chip. SRAM macros are realized with a bipolar technology, such as TTL, ECL, or I2L or with MOS technology, such as NMOS or CMOS. Bipolar SRAMs are relatively fast, having access times of 10 to 100 nsec. Power dissipation is also high, typically, 0.1 to 1.0 mW/bit. By contrast, MOS RAM access time is typically 100 nsec and power dissipation is 25 μW/bit. The combination of high circuit density, low power dissipation, and reasonable access time has led to the dominance of MOS technology in the manufacture of RAM. Hence, dual-port SRAM macros having high-speed buffers are widely used in devices and equipment necessitating high-speed and high performance, such as microprocessors, communication networks, facsimile machines, modems, etc.
Since the memory cells of SRAM macros take up a relatively large surface area on a single integrated (IC) chip, IC design engineers, in an effort to increase the number of memory cells on the IC chip, i.e., high density, and make the chip smaller, have focused on improving dynamic RAM (DRAM) macros or chips to make them suitable for high-speed, high performance devices and equipment. Currently, the ultimate in achieving high-density and compactness, is a DRAM macro capable of storing data in the single-cell array format where each memory cell uses a capacitor to store a charge and one transistor to gate it to sense amplifier circuits.
It is desirable that high-performance memories, such as DRAM macros, can be automatically generated and optimized for performance and size by using a computer program, e.g., a compiler program. The advantages of compiling DRAM macros are (1) a short design cycle; (2) a short time to market; (3) low cost; (4) compatibility with ASIC environment; and (5) flexibility on customized specifications, such as memory size, number of banks, data bandwidth, access time, cycle time, etc.
U.S. Pat. No. 6,002,633 issued to Oppold et al. on Dec. 14, 1999 describes a compiler program for synthesizing different configurations of SRAM. However, due to the uniqueness of DRAM macros, which is described below, the same methodology cannot be applied to generate DRAM macros. In fact, it is more difficult to make DRAM macros compilable than SRAM macros, due to the different parts and functions of DRAM macros which are not easily “growable”, as discussed below.
On-chip DC Generator System
Unlike an SRAM macro, a DRAM macro needs several voltage levels generated on-chip. These include, Vpp or the boosted wordline voltage (approximately 2.2 V), Vwl or the negative wordline voltage (approximately −0.5 V), substrate bias voltage (approximately −0.4 V), Vbg or bandgap reference voltage, Vref or DC reference voltage, etc. All these voltages are required to either boost the DRAM performance or enhance the charge retention time. The size of a DC generator system usually is custom designed depending on banking, refresh and pre-charge operations. These DC generator components are not needed for the SRAM macro.
Refresh Operation
Charge stored in the DRAM cells must be periodically refreshed, or otherwise, the data will be lost. The SRAM array is formed with cells where the data is latched in a cell formed by back-to-back inverters. Therefore, the data will never be lost, unless the power is removed.
The refresh operation in the DRAM is done either externally by a request from the memory controller or CPU, or internally by a refresh counter to generate refresh row address and by a refresh clock generator to determine when and which row needs to be refreshed. Therefore, as the DRAM size varies, or for a very different banking arrangement, the refresh scheme must be changed accordingly depending on refresh penalty and peak power consumption.
Power-on Circuit
For a DRAM macro during power-on, it is important to properly turn on each one of the on-chip generators in a certain sequence, so as to avoid any possibility that could lead to a latch-up problem. Normally, a power-on circuit is needed to handle the whole DRAM macro to coordinate the power-on sequence. However, the design of DC components to be used for a compilable DRAM must be able to sustain a minimum macro unit. For example, if 1 Mb is the smallest compilable DRAM unit, then at least one DC system is needed for each 1 Mb memory macro.
Banking Arrangement
In the past, DRAM has been inherently slower than SRAM. It has been proposed that one must take advantage of multiple bank techniques to double the DRAM speed to closely approximate the speed of SRAM. In other words, reading from one bank while simultaneously writing to another bank.
Other than the above-mentioned unique aspects of DRAM macros which make DRAM macros difficult to automatically generate and optimize for performance and size by using a compiler program, DRAM macros also share some of the same challenges as those of SRAM macros. For example, how to provide a clock timing which is tuneable by the array size, and how to provide a re-configurable data bandwidth to meet customer specifications.
Accordingly, there exists a need for a method and compiler for creating at least one array or bank unit of a DRAM macro of a high-performance DRAM memory system, such that electrical performance of the DRAM macro, including cycle time and access time, is optimized. It is preferred for the compiler to be able to accommodate a wide variety of customer specifications and to build DRAM macros having configurations which satisfy the wide variety of customer specifications.